9:00 AM – 12:00 PM, February 25, CSL 301
This session explores fundamental advances in integrated circuits, computer architectures, and large-scale systems that are shaping the future of technology, highlighting how progress across these levels is being jointly leveraged to address the performance, efficiency, and scalability challenges of next-generation platforms. The session showcases cutting-edge research spanning analog, mixed-signal, and RF circuits, accelerator and GPU architectures, in-memory and near-memory computing systems, hardware–software co-design, reliability and fault tolerance in cloud-scale deployments, and AI-enabled electronic design automation, offering a comprehensive view of how circuits, architectures, and systems are converging to enable transformative advances in computing and communication infrastructure.
Keynote Speaker – Prof. Mohammad Alian, Cornell University
Time: 9:00 – 10:00 AM
“Processing In and Near Memory to Power Next-Generation AI Inference Systems”
Abstract: The rapid rise of compound AI systems, most notably Retrieval-Augmented Generation (RAG), is fundamentally reshaping the structure of end-to-end inference pipelines. Modern Gen-AI inference increasingly extends beyond general matrix–matrix (GeMM) operations to include information retrieval and attention phases with extreme memory capacity and bandwidth demands. These memory-intensive stages make homogeneous, GPU-only systems increasingly inefficient for executing next-generation, planet-scale Gen-AI applications. Powering the next wave of Gen-AI systems requires architectural support not only for compute-intensive GeMM operations, where GPUs and TPUs excel, but also for data-centric execution. Processing-in-Memory (PIM) and Processing-Near-Memory (PNM) architectures provide a compelling path toward meeting the stringent bandwidth and capacity requirements of retrieval and attention phases in modern inference pipelines. In this talk, I present Dense-Retrieval Accelerator (DReX), a PIM/PNM-enabled, CXL-based memory architecture that seamlessly integrates with existing CPU/GPU systems to offload memory-intensive stages of the Gen-AI inference pipeline. We demonstrate the use of DReX to accelerate both retrieval and attention in RAG applications. DReX delivers orders-of-magnitude speedups for dense retrieval, translating into higher end-to-end accuracy, faster token generation, and support for significantly longer input contexts in RAG systems.
Biography: Mohammad Alian is an Assistant Professor in the Department of Electrical and Computer Engineering at Cornell University. He received his Ph.D. from the University of Illinois Urbana-Champaign. His research focuses on rethinking the traditional separation between the data-delivery hierarchy, including memory, storage, and networking, and compute, with the goal of enabling next-generation AI data centers. His work has been recognized with four Best Paper nominations, an Honorable Mention from IEEE Micro, a runner-up award in the Samsung Open Innovation competition, and an NSF CAREER Award. He is a member of the MICRO Hall of Fame.
Invited Student Speaker – Jonathan Zhou, Princeton University
Time: 10:00 – 10:45 AM
“End-to-end AI-Enabled Design of RF-to-THz Integrated Circuits”
Abstract: Design of RF, millimeter-wave, and sub-terahertz integrated circuits remains a highly manual and experience-driven process, heavily reliant on iterative techniques, rules of thumb, and predefined templates. This approach limits both design productivity and access to unconventional yet potentially superior solutions. In this talk, we present recent progress toward an AI-enabled, end-to-end RFIC synthesis framework that directly maps performance specifications to fabrication-ready circuit layouts.
The proposed methodology combines reinforcement learning with deep-learning-based inverse electromagnetic design to jointly explore circuit architecture, topology, device sizing, and on-chip passive structures. Rather than optimizing within fixed templates, the framework enables universal synthesis of electromagnetic structures and allows circuit architectures to emerge algorithmically. Fast, learned electromagnetic surrogate models replace expensive full-wave simulations, enabling efficient exploration of a vast, previously inaccessible design space.
Using this approach, we demonstrate fully automated synthesis of mmWave and sub-THz power amplifiers and low-noise amplifiers, including fabricated silicon prototypes spanning 30–120 GHz. The resulting designs often exhibit non-intuitive architectures and layouts, yet achieve state-of-the-art measured performance. These results point toward a new design paradigm in which AI serves not only as an optimization tool, but as a means for discovery in RFIC designs.
Biography: Jonathan Zhou is a Ph.D. candidate in Electrical and Computer Engineering at Princeton University, advised by Prof. Kaushik Sengupta. His research interests include AI-enabled design automation for RF, mmWave, and sub-THz integrated circuits, with a focus on reinforcement learning and inverse electromagnetic design for end-to-end RFIC synthesis.
Student Presentations
Time: 11:00 AM – 12:00 PM
Zihan Zheng: “Tileweaver: Weaving Tile-Level LLM Kernels from TileLang to FPGA”
Sriram Devata: “JigsawServe – Serving Compound Inference Systems on Datacenter GPUs”
Ryan Yuyang Fu: “Detector-in-Memory Architecture for Massive MIMO Signal Detection”
Manvi Jha: “Proof2Silicon: Prompt Repair for Verified Code and Hardware Generation via Reinforcement Learning”